The inventors herein have examined a flash memory as an example of a nonvolatile semiconductor memory device as follows.
For example, in a flash memory, a nonvolatile memory element having a control gate and a floating gate is used as a memory cell, and a memory cell can be constructed by a single transistor. For such a flash memory, the concept of a so-called “multi-value” flash memory for storing data of two or more bits per memory cell in order to increase storage capacity has been proposed. In such a multi-value flash memory, by controlling the amount of charges injected into the floating gate, the threshold voltage is changed step by step, and information of plural bits can be stored while being associated with a threshold voltage.
Further, in the flash memory, as the storage capacity increases, the chip size also increases. Consequently, it is requested to suppress increase in the chip size. For example, in the case of considering the chip size, there are many restrictions on the area of a memory array made by a plurality of memory cells disposed in a lattice state at crossing points between the word lines and the bit lines, so that attention has to be paid to the area of a Y-direct circuit in the memory array. A Y-direct circuit of a flash memory has, for example, a circuit configuration (refer to, for example, FIG. 4 which will be described later) employing the technique of a so-called single-end sense method.
The Y-direct circuit employing the single-end sense method has a configuration in which a sense latch circuit is disposed at one end of a global bit line, so that the circuit is employed for the purpose of reducing the area (reduction of the number of cells). Further, in the Y-direct circuit, for area reduction, a technique employing a so-called “one sense latch circuit+two SRAMs” configuration in place of the configuration of a data transfer circuit called a “one sense latch circuit+two data latch circuits” has been proposed. In the “one sense latch circuit+two SRAMS” configuration (refer to, for example, FIG. 6 which will be described later), two SRAMs are assigned to a plurality of sense latch circuits in each bank, data of an upper bit is stored in one of the SRAMs, and data of a lower bit is stored in the other SRAM.
A technique employing a configuration of a so-called AG-AND type (refer to, for example, FIG. 2 which will be described later) as the configuration of a memory array has been proposed. The memory array configuration of the AG-AND type is such that a MOSFET driven by a gate control signal is connected to the source side of each memory cell of the AND type and the source side is connected to a common source line via the MOSFET. In the memory array configuration of the AG-AND type, to reduce the area of the memory array, the number of bit lines is reduced to one per two memory cells.
The inventors of the present invention have examined the techniques employing the “one sense latch circuit+two SRAM” configuration and the memory array configuration of the AG-AND type for the Y-direct circuit of a flash memory and the memory array and, as a result, clarified the following.    (1) In a memory array configuration in which data is erased on a word line unit basis like the flash memory of the AG-AND type, when the number of bit lines is reduced, a problem occurs such that the unit of writing and the unit of erasing do not coincide with each other. Specifically, when the unit of writing is one page, the unit of erasing is two pages.    (2) The AG-AND type of the hot electron injecting writing method has a problem such that, if there is a depleted bit in a string, rewriting cannot be performed normally. Specifically, when a plurality of depleted memory cells (over-erased cells: threshold voltage of 0V or less) exist on the same bit line in a block, even if one of the depleted cells is selected and the threshold voltage is increased again to 0V or higher, current flows in the other depleted cells so that the threshold voltage of the depleted memory cell cannot be increased to 0V or higher.    (3) The “one sense latch circuit+two SRAMS” configuration has a problem such that the sequence of the “one sense latch circuit+two data latch circuits” configuration cannot be applied. For example, to assure a margin for data in a memory cell and a margin for write data, separate data buffers are necessary.
The inventors herein therefore paid attention to the erasing operation in the memory array configuration such that two pages correspond to and are connected to one word line and got an idea of considering pages to be subjected to erase verification determination and rewriting process and considering page addresses of blocks in the case of simultaneously erasing two or more pages in order to optimize the erasing operation and achieving higher processing speed.
An object of the invention is to provide a nonvolatile semiconductor memory device such as a flash memory realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended drawings.